- PhD defense : "Exploration of reconfigurable tiles of computing-in-memory architecture for data-intensive applications"
- Soutenance de thèse : "Exploration d'une architecture tuilée reconfigurable de mémoire calculante pour les applications gourmandes en données"
- A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
- Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture