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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units
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Soutenance de thèse "Modèle de programmation bas niveau pour architecture de calcul proche mémoire"
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<a href="https://www.mdpi.com/2079-9268/12/1/18">Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM</a>
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Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator
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Dynamic Compilation for Transprecision Applications on Heterogeneous Platform
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PhD defense : Methodology for code-optimization of memory data layouts by adaptation to high-performance-system architectures with complex memory hierarchies
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A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
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Data-layout optimization based on memory-access-pattern analysis for source-code performance improvement
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Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
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Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces
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Software Platform Dedicated for In-Memory Computing Circuit Evaluation
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Software Platform Dedicated for In-Memory Computing Circuit Evaluation