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  • A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications Thu, Jul 23, 2020
  • Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture Fri, Jan 10, 2020
  • Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces Tue, Apr 3, 2018
  • Software Platform Dedicated for In-Memory Computing Circuit Evaluation Wed, Dec 13, 2017
  • DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture Wed, Oct 5, 2016