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A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
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Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces
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Software Platform Dedicated for In-Memory Computing Circuit Evaluation
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DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture