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Latest Trends in Compiler Technology and Applications
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Cours de compilation en ligne : Twitch est-il un bon support ? Le public pour une chaîne sur la compilation est-il supérieur à 1 :-)
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Soutenance de HDR : Evolutions of the Software Flow for Automated Testing
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Fetch 2024 : Économie circulaire et Écoresponsabilité des systèmes embarqués : divorce dans le couple logiciel / matériel
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RISCV Lichee Console 4A mini laptop discovery
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Lessons during compiler course at UGA (Grenoble University)
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HybroGen winner of the first ESSC contest during ESWEEK
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Numérique frugal @ UGA
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New HygbroGen release, with computing in memory support (as well as AARCH64)
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Dedicated Instruction Set for Pattern-based Data Transfers: an Experimental Validation on Systems Containing In-Memory Computing Units
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Compiler Visual illustration using "SSA-based compiler design"
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PARMA DITAM proceedings available online
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Contribution à Fetch 2023
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OS installation on an OVH KS-5 using FreeBSD 13.1 via BYOI
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Évaluation de l’inférence d’un réseau de neurones sur une architecture C-SRAM (Computing SRAM)
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<a href="https://www.mdpi.com/2079-9268/12/1/18">Towards Integration of a Dedicated Memory Controller and Its Instruction Set to Improve Performance of Systems Containing Computational SRAM</a>
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How to work as compiler specialist with hardware architects
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FETCH 2022 une école d'hiver au printemps sur les Technologies de Conception des Systèmes Embarqués Hétérogènes
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Soutenance de thèse "Compiling Trees : combining Data Layouts and the Polyhedral Model"
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Towards a truly integrated vector processing unit for memory-bound applications based on a cost-competitive Computational SRAM design solution
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Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator
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Introduction to Dynamic Code Generation an Experiment with Matrix Multiplication for the STHORM Platform
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Proposition de stage : Évaluation de l’inférence d’un réseau de neurone sur une architecture de C-SRAM (Computing SRAM)
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Dynamic Compilation for Transprecision Applications on Heterogeneous Platform
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Recrutement : Compilation bas niveau / optimisation de code
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PhD defense : Methodology for code-optimization of memory data layouts by adaptation to high-performance-system architectures with complex memory hierarchies
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PhD defense : "Exploration of reconfigurable tiles of computing-in-memory architecture for data-intensive applications"
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A 35.6TOPS/W/mm² 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications
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Data-layout optimization based on memory-access-pattern analysis for source-code performance improvement
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Precision variable anonymization method supporting transprecision computing
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Toward Modeling Cache-Miss Ratio for Dense-Data-Access-Based Optimization
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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
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Keynote lors de la conférence COMPAS
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Automated Software Protection for the Masses Against Side-Channel Attacks
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Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces
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Software Platform Dedicated for In-Memory Computing Circuit Evaluation
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Fiche "Compilateur"
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Software Platform Dedicated for In-Memory Computing Circuit Evaluation
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DRC 2 : Dynamically Reconfigurable Computing Circuit based on Memory Architecture
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ComNet-IoT 2016 international workshop
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IoT symposium during ESWEEK
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Hardware Acceleration of Red-Black Tree Management and Application to Just-In-Time Compilation
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Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5
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deGoal a Tool to Embed Dynamic Code Generators into Applications
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Accélération Matérielle de la compilation à la volée pour les systèmes embarqués.
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Porting Different Compilation phases to Runtime.
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Efficient data driven run-time code generation