Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture
Roman Gauchi has presented a part of his work during the VLSI-SOC conference https://vlsi-soc.pe/ in Peru.
His work is in the context of “in memory computing”. This work explores the consequences of different tiling (memory cut) on the wirering interconnection and the impact on performance and power consumption.
Punch line :
« To achieve a large capacity IMC memory, by splitting the memory in multiple sub-tiles, we can achieve lower energy (up to 78% gain) and faster (up to 49% gain) IMC tile compared to a single large IMC memory instance.»
His article is now available on ieeexplore: https://ieeexplore.ieee.org/abstract/document/8920373 and soon a preprint on HAL
It seems that Roman (on the right) is able to master the evils that are inside “in memory computing” concepts !