Smart Instruction Codes for In-Memory Computing Architectures Compatible with Standard SRAM Interfaces
This paper presents the computing model for In-Memory Computing architecture based on SRAM memory that embeds computing abilities. This memory concept offers significant performance gains in terms of energy consumption and execution time. To handle the interaction between the memory and the CPU, new memory instruction codes were designed. These instructions are communicated by the CPU to the memory, using standard SRAM buses. This implementation allows (1) to embed In-Memory Computing capabilities on a system without Instruction Set Architecture (ISA) modification, and (2) to finely interlace CPU instructions and in-memory computing instructions.
Authors : Maha Kooli , Henri-Pierre Charles , Clement Touzet , Bastien Giraud, Jean-Philippe Noel
It was presented during the DATE 2018 (Design, Automation & Test in Europe) conference in Dresdes . https://www.date-conference.com/proceedings-archive/2018/ 2018
The preprint documents will appear soon on HAL :
- The full article : https://hal-cea.archives-ouvertes.fr/cea-01757656
- The presentation slides : https://hal-cea.archives-ouvertes.fr/cea-01757665
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