Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5

Tue, Apr 29, 2014

Accepted article in SAMOS XIV conference.

“Micro-architectural Simulation of In-order and Out-of-order ARM Microprocessors with gem5” Fernando A. Endo, Damien Couroussé and Henri-Pierre Charles

Link to the article: 2015-Endo-MicroArchitectural

Abstract: Heterogeneous multicore systems have gained momentum, specially for embedded applications, thanks to the performance and energy consumption trade-offs provided by inorder and out-of-order cores. Micro-architectural simulation models the behavior of pipe-line structures and caches with configurable parameters. This level of abstraction is well known for being flexible enough to quickly evaluate the performance of new hardware implementations, such as future heterogeneous multicore platforms. However, currently, there is no open-source micro-architectural simulator supporting both in-order and out-of-order ARM cores. This article describes the implementation and accuracy evaluation of a micro-architectural simulator of Cortex-A cores, supporting in-order and out-of-order pipelines and based on the open-source gem5 simulator. We explain how to simulate Cortex-A8 and Cortex-A9 cores in gem5, and compare the execution time of ten benchmarks with real hardware. Both models, with average errors of only 7 %, are more accurate than similar micro-architectural simulators, which show average errors greater than 14 %.